1. Field of the Invention
The invention relates to pulse width modulator-driven multiphase power regulators, and more particularly to control schemes and related architectures for improved efficiency at light load conditions.
2. Description of the Related Art
Multiphase voltage regulators provide a cost-effective power solution when load currents are too high to be readily supported by single-phase regulators. In a multiphase regulator system, the switching on of each channel is generally timed to be symmetrically out of phase with each of the other channels. Conventional multiphase regulators include multiple phase circuits or regulators coupled in parallel each including pulse width modulation (PWM) modulators. While multiphase voltage regulators can achieve relatively high power efficiency at heavy load, the efficiency decreases appreciably at light load conditions due to a higher ratio of switching, gate charge, and inductor core losses over the output power.
Certain microprocessors or central processing units (CPUs) include a mode select signal which is used as an external triggering signal to request a low power mode. The microprocessor asserts the mode select signal to a first state during normal operation when normal current or a relatively high load current is needed. The microprocessor asserts the mode select signal to a second state to indicate a low power mode to reduce load current and thus reduce power consumption. Certain microprocessors support the VR11 power specification by Intel Corporation (e.g., VR11.1) in which the microprocessor asserts a mode select pin PSI# (power state indictor) or the like to indicate normal or light load conditions. The “#” symbol appended to a signal name denotes negative logic in which PSI#=logic 1 (asserted high) for normal operation and PSI#=logic 0 (asserted low) for light load conditions. If the microprocessor or CPU does not provide a mode select pin or signal or the like, other load devices (e.g., system power management controller, regulator controller, etc.) may be configured to perform a similar function. In an alternative arrangement, the load current is simply measured by a current sensor or the like and a mode select signal is asserted when the current drops below a predetermined threshold for a predetermined amount of time.
There are several known schemes for improving power efficiency for multiphase voltage regulators. One scheme is referred to as phase dropping, in which one or more phases are simply “dropped” when a low load condition is requested or sensed as previously described. FIG. 1 is a timing diagram plotting the PSI# signal versus PWM signals PWM1-PWM6 for a six phase voltage regulator illustrating phase dropping for light load conditions. At a time t0, the PSI# signal is initially asserted high indicating normal operation in which pulses are asserted on the PWM1-PWM6 signals out of phase and in sequential order to ensure that each of the phases contribute to the load current. When the PSI# is asserted low at a subsequent time t1, the PWM2-PWM6 signals are turned off or otherwise tri-stated to drop or shut down phases 2-6 while the first phase 1 remains operating during the light load condition. When PSI# is once again asserted high at a subsequent time t2 to indicate a normal or otherwise heavy load condition, the voltage regulator returns to its normal operating mode in which the PWM2-PWM6 signals are reinstated to drive the load current.
It is desired to maintain the output voltage within specifications during phase dropping and reinstatement of dropped phases. The scheme illustrated in FIG. 1, in which several phases are immediately dropped and reinstated, may cause an undesirable glitch or abrupt change of the output voltage while transitioning between normal and low power modes. There are several other known ways to drop phases upon entering a light load condition to better maintain the output voltage within specifications. In another arrangement, a phase is not shut down until after the current through the output inductor of that phase drops to zero or some other predetermined low level. By slowly dropping phases at light load, the regulator controller can slowly increase the current in the remaining phase, resulting in relatively smooth transitioning. In this arrangement, however, multiple switching cycles are used to drop the phases, which results in more PWM cycles of switching, gate charge, and inductor core losses for the phases to be dropped. If the system enters and exits the light load condition at a highly repetitious rate, such as for typical CPU applications, this slow transitioning scheme may result in significantly lower power efficiency.
It is desired to provide a multiphase voltage regulator controller architecture and associated control methodology which provides improved power efficiency at low load currents even under highly repetitious mode switching conditions.